MemoryCanvas™ provides a unique approach to compilation of embedded memories. Existing commercially available solutions are cumbersome due to the complexity of managing thousands of lines of primitive code or unstructured scripts.
Spectral’s solution is a graphically driven floor planner that encapsulates all the compiler intent, the schematics, and layouts into a concise database that automatically generates memory instances. MemoryCanvas™ eliminates the need to write compiler software. The productivity of com-piler development is greatly enhanced by the tool’s easy-to-use, visually-driven feature.
Figure 1 MemoryCanvas™ accepts a graphical floorplan, schematic & layout leaf cells and special annotations as inputs and produces views for Simulation, LVS, DRC and P&R
- Graphically Driven Compiler
- Rapid Learning Curve
- Self-Documents the Compiler and Design
- Correct by Construction Assembly
- Supports All Memory Types
- Accepts ROM Pattern Files
- Views for Chip Verification & Integration
- Corporate Standard for all Compilers
- Process Independent and Portable
- Automatic Netlist for Characterization
- Central Database for Schematic & Layout
Example Schematic Floor Plan
“A picture is worth a thousand words”
MemoryCanvas™ accepts as inputs the schematic and layout leaf cell libraries as captured in the graphical floor plan. The relations of leaf cell placements is evident from the symbol/schematic driven floorplan (Figure 2). The block type designates whether they are arrays or single instantiations. Directives are attached to leaf cell elements in each block that guide MemoryCanvas™ in the overall instance assembly.
Example Compiled Instance Layout
MemoryCanvas™ can quickly produce a fully functional whole instance schematic
MemoryCanvas™ benefits the circuit design architect, layout designers, validation engineers, and compiler integrators. The floor plan provides an excellent means for designer and layout engineer to communicate assembly intent. The schematic and layout correspondence insures no mistakes in cell interfaces, signal directions and pitch matching constraints for all parameterization options. The easy-to-learn and exchangeable compiler format makes an ideal choice to standardize all corporate memory compiler development. LVS issues are minimized as correct-by-construction assembly between schematic and layout is assured while formal verification and netlist simulations insure functional compliance.
MemoryCanvas™ also supports the compiler characterization process. It automatically produces a configurable donut netlist(Fig 5), or a reduced Pi netlist. It integrates with existing netlist pruners/critical path methods. MemoryCanvas integrates seamlessly to existing commercial data collection and timing view engines.
MemoryCanvas™ is ideally suited to be used for producing instance families for complex memories such as Embedded Cache and Memories for whole standard parts. Through integration with standard EDA tools that support routing and chip assembly, users can quickly implement the memories and interfaces to the entire chip infrastructure for productivity improvement.