MemoryRx™

MemRx™ is a MBIST (Memory Built-In Self-Test and Repair) solution that enables comprehensive testing of multiple memory modules in a SoC (System-On-Chip). With a rise in design complexity and Memory capacity for advanced ASIC designs, it is imperative to accurately diagnose, test, and repair Memory. This easy-to-use solution reduces the complexity and cost of testing embedded memories by making trade-offs between test time and coverage.

Key Features


-> Multiple BIST Controllers
-> Built-In ECC
-> Multiport SRAMs, TCAMs, and RFs
-> Programmable Test Algorithms
-> Single Error-Correcting and Double Error-Detecting
    Codes on memories
-> Memory Column Repair
-> Serial error bus and remote address / data generators to
    remove hundreds of wires from MBIST
-> Compatibility with third-party MemoryIP
-> User-Friendly GUI

Figure 1: MemoryRx MBIST Controller

Product Description

MemoryRx is a complete solution for Memory BIST, diagnosis, repair, and logic synthesis for Memory Instances on an SoC. The diagnosis information locates the faulty bit position in a Memory word. For specialty memories like TCAMs, MemoryRx will fully diagnose false matches, missed matches, and faults in MATCH_LINE vectors. Figure 1 (left) shows a system with multiple MBIST controllers on a chip. MemoryRx automatically groups compatible Memories onto MBIST controllers. Each MBIST Controller and the Memories it controls are grouped within a Verilog wrapper. 

Figure 2 - MemoryRx GUI

The Master MBIST Controller synchronizes pattern generation and test such that the amount of power consumed during test is minimized. The tool also generates a JTAG wrapper for the controller modules. MemoryRx supports the IEEE Standard JTAG Controller, which will eliminate hundreds of wires that are normally required to send out: fault diagnosis data, Read/Write/Assist margins, sleep modes, and voltage settings between MBIST and the mission hardware. A serial JTAG bus of only five signals is required in this implementation.

Pin Diagram Description

Figure 3 shows the input/output for running MemoryRx. In addition to the visible pins there are busses for Memory commands, bad memories, bad ports, bad addresses, bad bit numbers, bad port operations, and the number of unrepairable errors. Furthermore there are pins for bad bit value, to indicate if the memory is unrepairable, and to indicate a cache miss.

Figure 3 - Simple MBIST State Diagram

Benefits

MemoryRx supports all standard test algorithms, such as MARCHC-, MARCHA, MARCHB, MARCHX, MARCHY, MARCHML (for TCAMs), and Weak Bit Cell Tests. The program also provides a straightforward approach to adding custom march tests to enhance fault coverage. MemoryRx currently supports generating a complete command deck for synthesis/timing closure using the Cadence Genus logic synthesizer.

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Contact
  • Spectral Design & Test Inc,
    64 East Main Street, Somerville,
    New Jersey 08876, United States
  • +1 (908)-393-2500
  • support@spectral-dt.com

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