Design IP

MemoryCanvas™
MemoryCanvas™ is a patent pending visual memory compilation tool that eliminates the need to write thousands of lines of complex source code that is inherent to complex memory compiler solutions. The tool is built on top of commercial schematic and layout databases and can be very easily portable to the customer’s memory design eco system. Additionally, MemoryCanvas has built-in features to optimize device sizes and can write out verification and characterization netlists. Our memory compilation tool has been used to compile simple Register Files to extremely complex full-ternary CAMs.

For datasheets & benchmark data please contact sales@spectral-dt.com

MemoryTime™
Memorytime™ is a unique modeling & characterization tool targeted at embedded memory designs. Circuit designers can compile testvectors that can be used either with full spice netlists or critical paths to obtain critical timing and power parameters. Characterized timing data can be formatted to industry standard timing views. Timing data collection is facilitated by a very efficient job control system for job queing and parallel execution. The tool has a unique capability to create test vectors based on the interfacetimeing and validate circuit functionality using behavioral models and full spice netlists. Memorytime™ supports memory compilation capabilities for both Modeling and Characterization and incorporates industry standard embedded memory models for SRAMs, ROMs, CAMs & Multi-Port Register Files.

For datasheets & benchmark data please contact sales@spectral-dt.com

MemoryIP™
MemoryIP™ is a collection of silicon proven embedded memory architectures that can be targeted to multiple technologies. SOC designs typically require RAMs, ROMs, Register-Files that are configurable based on a range of words & bits-per-word. MemoryIP comprises of source code that can generate a Single Port RAMs, Dual-Port RAMS, Single Port Register Files, Diffusion & Metal Programmable RAMs in conjunction with MemoryCanvas & MemoryTime point solutions. MemoryIP enables memory library developers to efficiently target SpectralRAM, SpectralRF & SpectralROM designs to multiple process technologies. Alternatively memory compiler developers can mix and match MemoryIP designs with their own proprietary designs. Using MemoryIP Spectral's unique Memory Development platform, memory designers can significantly reduce memory compiler or  memory instance development time.

For datasheets & benchmark data please contact sales@spectral-dt.com

Design For Test (DFT)

Entropy™
Entropy™ is a patent pending test point insertion tool that is based on a very unique statistical approach to identifying sections of a sequential/combinational circuits that are very hard to test. The tool adds testpoints to the circuit under test resulting in a radical cut down in test-volume and improvement in fault coverage using industry standard ATPG solutions. Entropy supports state-of-the-art design circuits and methodologies that are used to manufacture high capacity, low power & high performance chips in the 65nm and lower geometries.

For datasheets & benchmark data please contact sales@spectral-dt.com